Linux command
iverilog 命令
文本
复制后可按需替换文件名、目录或参数。
常用示例
Compile Verilog file
iverilog -o [output] [input.v]
Compile multiple files
iverilog -o [output] [file1.v] [file2.v]
Specify top module
iverilog -s [top_module] -o [output] [input.v]
Generate VCD output
iverilog -o [output] [input.v] && vvp [output]
Include directory
iverilog -I [include_dir] -o [output] [input.v]
Define macro
iverilog -D[MACRO=value] -o [output] [input.v]
说明
iverilog is the Icarus Verilog compiler. It compiles Verilog HDL to simulation executables. The tool supports IEEE Verilog standards. Output runs with vvp simulator for verification and testing.
参数
- -o _FILE_
- Output file name.
- -s _MODULE_
- Specify top-level module.
- -I _DIR_
- Add include directory.
- -D _MACRO_
- Define preprocessor macro.
- -g _STANDARD_
- Verilog standard (2001, 2005, 2009, 2012).
- -t _TARGET_
- Target format (vvp, null).
- --help
- Display help information.
FAQ
What is the iverilog command used for?
iverilog is the Icarus Verilog compiler. It compiles Verilog HDL to simulation executables. The tool supports IEEE Verilog standards. Output runs with vvp simulator for verification and testing.
How do I run a basic iverilog example?
Run `iverilog -o [output] [input.v]` in a terminal, then adjust file names, paths, flags, or remote targets for your system.
What does -o _FILE_ do in iverilog?
Output file name.