Linux command
yosys 命令
文本
复制后可按需替换文件名、目录或参数。
常用示例
Run synthesis on Verilog file
yosys -p "synth -top [module]" [design.v]
Start interactive shell
yosys
Execute script file
yosys -s [script.ys]
Synthesize and output to file
yosys -p "synth -top [module]" -o [output.json] [design.v]
Quick synthesis
yosys -S [design.v]
Run TCL script
yosys -c [script.tcl]
List available commands
yosys -H
Get help for command
yosys -h [synth]
说明
yosys is an open source framework for RTL synthesis. It reads Verilog hardware description language and synthesizes it to gate-level netlists for various target technologies. The tool provides an interactive shell with numerous commands for reading designs, elaboration, optimization, technology mapping, and writing outputs. Synthesis flows are defined through script files or command-line arguments. Supported input formats include Verilog, RTLIL, and Liberty. Output formats include BLIF, EDIF, JSON, Verilog, and various FPGA-specific formats. The tool supports plugins for extending functionality. Yosys is widely used in open-source FPGA toolchains including Lattice iCE40 and ECP5 flows with nextpnr.
参数
- -s _scriptfile_
- Execute commands from script file.
- -c _tclfile_
- Execute TCL script file.
- -p _command_
- Execute command(s).
- -o _outfile_
- Write design to file on exit.
- -f _frontend_
- Frontend for input files.
- -b _backend_
- Backend for output file.
- -m _module_
- Load plugin module.
- -l _logfile_
- Write log to file.
- -q
- Quiet operation (errors only).
- -v _level_
- Log verbosity level.
- -t
- Add timestamps to log.
- -S
- Shortcut for synth command.
- -H
- Print command list.
- -h _command_
- Help for specific command.
- -Q
- Suppress banner.
- -T
- Suppress footer.
FAQ
What is the yosys command used for?
yosys is an open source framework for RTL synthesis. It reads Verilog hardware description language and synthesizes it to gate-level netlists for various target technologies. The tool provides an interactive shell with numerous commands for reading designs, elaboration, optimization, technology mapping, and writing outputs. Synthesis flows are defined through script files or command-line arguments. Supported input formats include Verilog, RTLIL, and Liberty. Output formats include BLIF, EDIF, JSON, Verilog, and various FPGA-specific formats. The tool supports plugins for extending functionality. Yosys is widely used in open-source FPGA toolchains including Lattice iCE40 and ECP5 flows with nextpnr.
How do I run a basic yosys example?
Run `yosys -p "synth -top [module]" [design.v]` in a terminal, then adjust file names, paths, flags, or remote targets for your system.
What does -s _scriptfile_ do in yosys?
Execute commands from script file.